The Anti-Tamper Digital Clocks Diaries
The Anti-Tamper Digital Clocks Diaries
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32. The equipment for detecting voltage tampering as outlined in declare 30, whereby the means for triggering the suggests for analyzing takes advantage of a clock edge at an finish of the Consider time period to result in the suggests for assessing.
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an evaluate circuit, triggered via the clock, that works by using the primary plurality of delayed monotone indicators or the next plurality of delayed monotone alerts to detect a clock fault.
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What on earth is claimed is: 1. A method for detecting clock tampering, comprising: offering a plurality of resettable delay line segments, whereby resettable hold off line segments involving a resettable hold off line segment associated with a least hold off time as well as a resettable delay line segment affiliated with a highest delay time are Just about every affiliated with discretely escalating hold off times;
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four. The method for detecting clock tampering as described in assert 1, whereby the Examine circuit decides no matter if the quantity of ones inside the plurality of delayed monotone alerts differs from a water stage quantity by over a predetermined threshold.
38. The equipment for detecting voltage tampering as defined in declare 37, wherein the resettable hold off line segments are reset during a reset time period, whereby the reset time frame is previous to the evaluate time frame.
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A monotone sign is presented through a clock Consider time frame connected to a clock. The monotone sign is delayed using each with the plurality of resettable delay line segments to crank out a respective plurality of delayed monotone indicators. The clock is accustomed to trigger an Appraise circuit that utilizes the plurality of delayed monotone signals to detect a clock fault.
A different element of the invention may perhaps reside within an equipment for detecting voltage tampering, comprising: signifies for supplying a monotone signal all through an Examine time; implies for delaying the monotone signal using a plurality of resettable hold off line segments to crank out a respective more info plurality of delayed monotone alerts getting discretely raising delay instances involving a minimum delay time plus a highest hold off time; and suggests for utilizing the clock to bring about an Assess circuit that employs the plurality of delayed monotone signals to detect a voltage fault.
The current invention relates commonly to detecting tampering With all the clock and/or supply voltage of the processor.